1. Field of the Invention
The present invention generally relates to a RFID device having a nonvolatile ferroelectric memory, and more specifically, to a technology of regulating bit line capacitance to optimize a bit line sensing margin and to minimize power consumption.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and preserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the high residual polarization characteristic of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
A common RFID device having a nonvolatile ferroelectric memory consumes a large amount of power resulting in a decrease of available power voltage.
At a read mode, the optimum sensing voltage margin is required to perform sufficient charge distribution between a cell capacitor and a bit line in the nonvolatile ferroelectric memory.
Since the nonvolatile ferroelectric memory uses a hysteresis loop, the sensing voltage margin becomes smaller and unable to perform a normal operation when the bit line capacitance is too small or too large.
That is, when the bit line capacitance is too small, a sufficient destructive operation cannot be performed in the charge distribution between the cell capacitor and the bit line.
Meanwhile, when the bit line capacitance is too large, the destructive operation is sufficiently performed in the charge distribution between the cell capacitor and the bit line. However, a development voltage is too small to perform a normal amplification operation.
As described above, since unit cells connected to a plurality of word lines are connected to one bit line, the intrinsic capacitance of the bit line is smaller than that of the cell capacitor. As a result, it is impossible to secure the optimum sensing voltage margin to the bit line in the charge distribution between the cell capacitor and the bit line.